Why did TSMC avoid high-NA EUV until 2029?
TSMC says it will hold off on using ASML’s most advanced high-NA EUV machines—systems that reportedly cost €350M+ apiece—for production through 2029, primarily to save money.
The decision is notable because next-generation EUV tools are expected to tighten the link between leading-edge process nodes and the ability to ramp volume production. By delaying the move to the most advanced equipment, TSMC is effectively choosing a cost/benefit trade-off: pay for scarce, extremely expensive capacity later, rather than immediately.
What TSMC is trying to optimize
From the information available, the underlying logic appears to be financial efficiency. High-NA EUV is positioned as a major step forward for patterning capability, but the need and readiness for it can vary by node strategy, customer demand, and the timing of design wins.
How this fits with TSMC’s broader roadmap
TSMC has also been laying out a process technology roadmap through 2029, aiming to launch new nodes on a regular cadence. The hold on high-NA EUV suggests TSMC will still advance manufacturing capability, but will manage the capital intensity of its equipment purchases until later in the decade.
If the delay holds, downstream chipmakers and customers may see longer-term implications for when the most advanced lithography benefits fully show up in high-volume silicon. For investors and partners, the key question becomes whether the postponed tool adoption affects performance, yield, or time-to-ramp for leading-edge products—or whether TSMC can meet near-term targets with less-capital-intensive equipment.